The purpose of an input protection circuit is to protect input gates, diffusions, metal lines, and other components from the potentially destructive effects of large electrostatic discharge (ESD) voltages applied to an input pad. Input protection circuits for CMOS integrated circuits must also prevent latchup--a circuit condition in which parasitic bipolar transistors short circuit the device's power supply and cannot be turned off without turning off the power supplied to the entire circuit.
Input protection circuits are typically formed along the periphery of semiconductor circuits, generally next to the input pads of the circuit. Each input protection circuit couples an input pad to circuitry in the interior portion of the semiconductor circuit.
Many different input protection circuits exist. Referring to FIG. 1, most such circuits use a combination of resistors, diodes and MOSFETs.
Input Resistors. As shown in FIG. 1, most prior art input protection circuits use a series input resistor RI to reduce the ESD (electrostatic discharge) voltage by dropping some of the voltage across the resistor. The input resistor also reduces the latchup current. The value of the input resistors used in the prior art ranges from as high as 2k ohm to as low as 20 ohms.
A well-known problem associated with the use of input resistors is an input RC delay. In particular, the capacitance of the metal line from an input pad to an input gate is typically 1 to 2 pf (picofarads). With an input resistance between 1K and 2K ohms, the input RC delay will between 1 and 4 nanoseconds. For a high speed part with a 10 to 20 nanosecond access time, this delay is not acceptable. Therefore smaller input resistors, in conjunction with one or more diodes, must be used in high speed circuits to absorb ESD voltages. As will be described below, the present invention allows the input resistor RI to be either completely eliminated or reduced to a nominal value.
Input Diodes. Diodes are often used to provide a nondestructive path for ESD currents. The parasitic series resistance of the diodes, however, can reduce the amount of current shunted by the diodes. To reduce this resistance, large area diodes are sometimes used, which increases the die area and capacitance of the input protection circuit. Epitaxial layers are also used in some circuits to reduce the parasitic resistance.
ESD Test Circuit. Referring to FIG. 2, input protection circuits are typically tested using a test circuit such as circuit 22. In the test circuit 22 shown, a storage capacitor C1 of 200 picofarads is used, with a series resistor RT of 1500 ohms. Thus the time constant of this test circuit is 300 nanoseconds.
The test circuit 22 is used as follows. Voltage source V1 is generally a controllable voltage source which can generate any selected voltage level in a predefined range, such as -5000 to +5000 volts. A selected voltage level, such as +2000 volts is placed on capacitor C1 by operating the voltage source V1 at the selected voltage level and then temporarily closing switch SW1. Once the capacitor C1 is charged, the stored charge is delivered to the PAD by opening switch SW1 and then closing switch SW2.
The test circuit shown in FIG. 2 is sometimes called the "human body" model, because it simulates the effect of a person accumulating a static charge and then touching an integrated circuit. Another commonly used test circuit, sometimes called the machine model, eliminates resistor RT in the test circuit 22, simulating the coupling of an integrated circuit to a machine with an accumulated static charge.
Referring again to FIG. 1, most input protection circuits use only a single input diode (or several parallel diodes of the same type) to absorb ESD voltages. However, problems with the use of a single input diode can arise when an ESD voltage reverse biases the diode. The diode clamps the input voltage at its reverse break down voltage. Unfortunately, the reverse break down voltage of the diode is typically higher than the breakdown voltage of the device's transistor gates. Therefore the input gates may be destroyed before the diode reacts.
Complementary Input Diodes. FIG. 3 depicts the schematic of an input protection circuit which is similar to the one in FIG. 1, but which uses two complementary input diodes D1 and D2 and two MOS transistors M1 and M2.
FIG. 3 also depicts a portion of the bipolar model, with transistors Q1 and Q1, for the CMOS circuit in FIG. 3. The primary motivation for using two complementary input diodes and their associated transistors is to facilitate the absorption of both positive and negative voltage ESD voltages and currents.
More specifically, upon the occurrence of an ESD, one of the two diode and MOS transistor pairs (depending on the polarity of ESD voltage) will turn on at the forward turn on voltage of the diode (approximately 0.7 volts). The bulk of the ESD current will go through the forward biased diode.
If the ESD voltage rises fast enough, the reverse biased diode will absorb some, but not all of the current, thereby helping to prevent the input voltage from reaching the gate oxide breakdown voltage of the device's transistor gates. For fast input voltage rise times, characteristic of ESD, the response time of the forward biased diode will be too slow to keep the input voltage near 0.7 volts, and therefore the breakdown voltage of the reverse biased diode will be reached. Fortunately, the breakdown voltage of gated diodes is lower than the gate oxide breakdown voltage. Therefore the reverse biased diode will absorb a portion of the ESD current and will help to protect the CMOS gates of the protected circuit. In addition, one of the two parasitic lateral bipolar transistors Q1 or Q2 will be turned on by the ESD input voltage, causing current to flow under the gate oxide of corresponding MOS transistor.
FIG. 4 shows a profile of a typical implementation of the input protection circuit shown in FIG. 3. FIG. 4 also shows the full bipolar model for the circuit, including two lateral bipolar transistors Q1 and Q2, and two vertical bipolar transistors Q3 and Q4. Note that D1 in FIG. 3 represents the PN junction between the input signal line 34 and N-well 30 in FIG. 4, and that D2 in FIG. 3 represents the NP junction between the input line and the substrate 32.
There are two serious disadvantages of the input protection circuit shown in FIGS. 3 and 4: destruction of the gate oxide 52 or 54 of M1 or M2 caused by shunting large ESD currents through the lateral parasitic bipolar transistor Q1 or Q2, and a latchup problem (also called a snap-back voltage problem) associated only with positive ESD voltages.
The gate oxide problem occurs in the following way. A positive ESD voltage will turn on bipolar transistor Q1 and a negative ESD voltage will turn on bipolar transistor Q2. Significant amounts of current will be shunted by the enabled transistor Q1 or Q2 along a path that is directly below the corresponding gate oxide 52 or 54. The high current densities near the surface of the substrate, caused by Q1 or Q2 shunting ESD currents, can heat and destroy the neighboring gate oxide 52 or 54.
Referring to FIG. 4, the snap-back problem occurs as follows. When a positive ESD voltage is encountered, the diode comprising the emitter-base junction of Q3 is forward biased, turning on vertical bipolar transistor Q3. As the ESD voltage rises, this will cause the voltage on the substrate node 32 to rise, causing transistor Q2 to turn on. When Q2 turns on, an SCR condition exists with transistors Q3 and Q2 both drawing current from the input signal line 34. As a result, the input voltage can be pulled below Vcc, which is considered to be an undesirable result. The sudden voltage drop on the input signal line caused by transistor Q2 being turned on is herein called a "snap-back" effect. At even higher current levels, true latchup can occur due to the triggering effect of this input SCR on other parasitic bipolar transistors.
In summary, the input protection devices currently in use have been less than satisfactory because they provide insufficient protection against large electrostatic discharges.
It is therefore a primary object of the present invention to provide an improved input protection device that can absorb large ESD voltages and currents and avoids the problems of gate oxide destruction and snap-back associated with prior art input protection circuits using complementary input diodes.
Another object of the present invention is to provide an input protection circuit using complementary input diodes which protects MOS and CMOS gates from even momentary exposure to voltages sufficient to destroy such gates.